30Verification

Keep a tick divider's phase across pauses

Problem

Intended behavior. TickDivider marks every fifth enabled cycle. phase counts enabled cycles from 0 to 4 and wraps. On an edge with en high it advances, and on an edge with en low it keeps its value. tick is high in a cycle where en is high and phase is 4. A pause therefore delays the next tick but does not restart the count of five. Reset clears phase.

Current behavior. Ticks are right while en stays high. After a pause, the next tick comes later than it should.

Your task. Use the waveform to find what happens to phase during a pause, and fix the design. Keep the ports, wrap, the tick line, and the public bench.

Read and predict

The public bench records a waveform. It drives 7 enabled cycles, a 3-cycle pause, and 10 more enabled cycles, and prints TICK in cycle n for each cycle in which tick is high, numbering the bench's cycles from 1. Then it copies the VCD to dump.vcd.

Before running, count enabled cycles and predict the cycle numbers of all three ticks for a correct divider. Then run the starter and compare the TICK lines with your prediction.

Read the waveform

Find io_en, phase, wrap, and io_tick. phase is a register, so it changes only at rising edges. Look at the edges during the pause, while io_en is low, and compare phase just before the pause with phase when io_en rises again. Then find the branch in the code that produces what you see.

Completion check

• tick is high on the 5th, 10th, 15th, ... enabled cycle, counting across pauses of any length.
• A pause that begins while phase is 4 moves the tick to the next enabled cycle, and tick stays low while en is low.
• Reset clears phase at any point.

Hints

Variation

Bind io.en && wrap to a val named fire and drive tick from it. Predict whether the TICK lines change, then inspect whether the waveform retains fire as a separate name or only the equivalent tick signal.