Chisel Practice

Read a Chisel module as a Scala class that builds a circuit, tell the connection := apart from a Scala name, predict what the testbench prints, run it, then change one parameter and see a different circuit.

Tell a one-bit Bool from a multi-bit UInt, apply the bitwise, bit-field, Cat and reduction operators to an 8-bit value by hand, run the operator example, see what shifts, arithmetic and comparisons build and how wide their results are, then build a parity frame.

Give a port a width with .W, read the width Chisel assigns to a literal, follow a signed value through a connection and a cast, then see why + loses a carry that +& keeps.

Choose between values with Mux and when, give a Wire a default, read the last-connection-wins rule off a trace, and see what happens to a path nothing drives.

Choose among many inputs with MuxCase, MuxLookup, PriorityMux and Mux1H, and decide which one a selection calls for by how its selectors behave.

Update a register only under a when and let it hold otherwise, decide which registers a reset changes from how each was created, see that the implicit reset acts at a clock edge, and write priority as source order.

Delay a signal by one edge with RegNext and by two with a second one, build a rising-edge detector from the delayed copy, then read reset, pokes, and register changes off a recorded waveform.

Group named fields in a Bundle and indexed elements in a Vec, read the bit layout that asUInt and asTypeOf follow, tell a Scala index from a hardware index, and use Flipped to put one interface declaration on both ends of a link.

Place a module inside another with Module(new ...), drive every child input, build a family of definitions from one parameterized class with require and desiredName, call a module through a companion apply, and read a generator written with for and def by counting what it built.

Give each state a name with ChiselEnum, hold it in a register, branch on it with switch and is, convert between an enum and raw bits safely, and read the width Chisel picked.

Turn a written requirement into ports, a register with a reset value, a when chain whose order is the priority, and a wrapping add, keep the functional clear apart from the implicit reset, and check the design against a cycle table before grading.

Read-only tables with VecInit and Counter, the combinational-read Mem, the synchronous-read SyncReadMem with its one-cycle latency and undefined-read cases, write masks and the SRAM API, and how to choose between them.

Describe an interface as a Bundle, connect two of them in bulk with <>, see what happens to a field with no partner, and run a ready-valid link with Decoupled.

Separate Scala type parameters and their upper bounds from value parameters, then use type templates, configuration objects, optional ports, and by-name module arguments to build related circuits.

Print from inside the circuit with printf and the cf interpolator, tell hardware printing from elaboration-time println, and read the signal names the compiler gives your vals.

Read a failed expectation down to the step that produced it, wait for an event without hanging the test, and use the idle-cycle timeout to tell a slow design from a stuck one.