10Verification

Give every lane its own unit

Problem

Intended behavior. LaneDistance computes four independent absolute differences, d(i) from x(i) and y(i), through AbsDiff children. With x = 10, 50, 200, 7 and y = 3, 80, 200, 9, the lanes must report 7, 30, 0, and 2.

Current behavior. The starter compiles and runs, but all four lanes print 2, and only one ELABORATE AbsDiff line appears before them.

Task. Find the defect in LaneDistance and fix it. AbsDiff itself is correct; keep its body and every port unchanged.

Read the starter

Count how many times Module(new AbsDiff) executes during elaboration. Then read the for loop and list every connection it makes to unit.io.a across the four iterations, in order.

Predict before running

Predict the number of ELABORATE lines and the four lane values for the starter, and explain why every lane shows the value of one particular lane. Then predict both observations for a corrected design.

Run and explain

The starter elaborates one AbsDiff. The loop runs four times, but each iteration connects the same child inputs, and the last connection wins: the child sees x(3) and y(3), and every d(i) reads its single output, 2. A corrected design prints four ELABORATE AbsDiff lines and then 7, 30, 0, and 2. The number of instances is decided during elaboration; nothing in simulation can make one instance compute four answers at once.

Completion check

Each lane reports the absolute difference of its own pair for any inputs, whether x(i) is larger, smaller, or equal.
Changing one lane's inputs never changes another lane's output.
The circuit contains one AbsDiff per lane.

Progressive hints

Hint 1

Module(...) places one instance each time it executes. A loop that follows the call reuses that instance; it does not copy it.

Hint 2

The instance must be created once per iteration so that each lane's connections reach a different child. Only the position of one line needs to change.

Concept

A child module is hardware, not a subroutine. Reusing one instance in a loop does not time-share it: Chisel collects all connections to its inputs and keeps the last. Parallel results need parallel instances, and the generator's Scala code decides how many exist.

Transfer experiment

Imagine the ports grew to Vec(8, UInt(8.W)) and the loop to eight iterations. Predict the ELABORATE count for the defective and corrected designs, and which lane's value the defective one would print everywhere.