About code0.HDL
What code0.HDL covers
code0.HDL is an educational site for three hardware description languages — Verilog, Bluespec SystemVerilog (BSV) and Chisel.
Each chapter includes a runnable example. The example compiles and runs on the page you are reading. Simulation output appears in a terminal, and where a design produces a VCD, the result can be inspected as a waveform.
The text is written in English and Korean. Both versions share the same example source, so the code executed does not differ between languages. Only an example's comments are shown in the documentation language.
How the content is written
The explanations here are written for code0.HDL. They draw on the language specifications and the official tool documentation, and are not an attempt to restate those documents sentence by sentence.
- Language specifications and official tool documentation are used as references.
- The BSV chapters follow the subject structure of the BSV Language Reference Guide. The explanations and runnable examples are written to suit code0.HDL's own learning sequence.
- The explanatory structure, the examples, the comments and the order of study are written here.
- Where material from another source is quoted or reworked, the page says so, and the original licence is recorded on the licences page.
- Explanations and examples are checked against the actual behaviour of the tool versions this site uses.
Execution environment
Verilog and BSV run in browser Workers, using Icarus Verilog and BSC WebAssembly. The code stays in the Worker; Stop ends the job and discards its temporary files. Browser jobs have a two-minute deadline, a 1 MiB output limit and a 4 MiB limit for the returned VCD. Unsupported commands or browser failures are not sent to the server. Server execution is disabled for both languages. BSV examples that link native C functions through BDPI require a local toolchain.
Chisel Run uses CheerpJ 4.3 with Java 17 in a fresh browser iframe. The first Run downloads the Java runtime from the Community CDN and the pinned Chisel JARs from this site. Tabs take turns using the runtime; Stop removes the current iframe. Startup and preparation each have a 120-second watchdog; compilation and simulation each have a 180-second watchdog. A stalled job is retried once in a fresh iframe, never on the server.
Practice Submit also runs on your device. It uses an observation testbench that contains test inputs and a check sequence, but no expected outputs. Only the resulting observation trace is sent to this site. The server executes no code: it compares that trace with private expected values and reports the first mismatch. Stop cancels the browser job or pending submission. Drafts and solved state stay in this browser.
The comparison API allows 12 requests per minute per client IP and accepts at most 1 MiB of JSON. Browser input files remain limited to 12 files and 256 KiB total. Chisel uses Chisel 6.7.0 and chiseltest 6.0.0; Verilog and BSV simulate with Icarus Verilog. Expected values and reference solutions are not downloaded.
These checks help you learn; they do not certify that an untrusted browser executed a particular program. See the privacy page for how observation traces are handled.
An independent project
code0.HDL is an independent educational project.
It is not affiliated with Bluespec, Inc., it is not Bluespec's official documentation site, and nothing here implies endorsement or approval by Bluespec, Inc. or by any other tool vendor. Language, tool and product names are used to identify what is being explained.