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code0.HDL

Choose a language to learn

One textbook per language, read from the first chapter or opened at the section you need. The fundamentals are shared by all three.

BSV

Design concurrent hardware with rules

Design concurrent behaviour with rules and interfaces.

What you build
  • Counters and state machines whose updates are atomic rules
  • Modules that expose methods through interfaces and compose into a design
  • FIFO pipelines whose readiness the compiler schedules for you
Before you start
Registers, clock edges, and what a combinational circuit is. No other HDL is required.
  1. A module and its interface
  2. Bool, Bit and pure functions
  3. Types, widths and explicit conversion
  4. Selection, case, and the don't-care value
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Verilog

Learn RTL through signals and clocks

Design combinational and sequential circuits with signals and RTL.

What you build
  • Combinational blocks from continuous assignments and vectors
  • Clocked registers and state machines with reset
  • Testbenches that drive inputs, print results, and dump a waveform
Before you start
Binary numbers and the idea of a clock. No other HDL is required.
  1. A module, its ports, and assign
  2. Vectors, bit selects and operators
  3. Literals, signed values and expression width
  4. Nets, variables and the combinational always
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Chisel

From circuits to hardware generators

Design parameterised circuits with Scala-based generators.

What you build
  • Modules whose ports and logic are built from Chisel hardware types
  • Registers, bundles, and vectors wired into sequential designs
  • Generators that produce a family of circuits from one parameterised class
Before you start
Registers and clock edges. Scala is introduced where each chapter needs it. No other HDL is required.
  1. A Module, its IO, and the := connection
  2. Bool, UInt, and the operators
  3. Widths, SInt, and arithmetic
  4. Mux, when, Wire, and a default for every path
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Fundamentals

Hardware fundamentals

Bits, logic, state and time, with experiments you can operate in the page. No HDL is needed yet; each language course says which chapter it builds on.

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