Choose a language to practice
Problems follow each course's chapters. Your drafts and solved problems stay in this browser.
BSV
Design concurrent hardware with rules
Design concurrent behaviour with rules and interfaces.
- What you build
- Counters and state machines whose updates are atomic rules
- Modules that expose methods through interfaces and compose into a design
- FIFO pipelines whose readiness the compiler schedules for you
- Before you start
- Registers, clock edges, and what a combinational circuit is. No other HDL is required.
Verilog
Learn RTL through signals and clocks
Design combinational and sequential circuits with signals and RTL.
- What you build
- Combinational blocks from continuous assignments and vectors
- Clocked registers and state machines with reset
- Testbenches that drive inputs, print results, and dump a waveform
- Before you start
- Binary numbers and the idea of a clock. No other HDL is required.
Chisel
From circuits to hardware generators
Design parameterised circuits with Scala-based generators.
- What you build
- Modules whose ports and logic are built from Chisel hardware types
- Registers, bundles, and vectors wired into sequential designs
- Generators that produce a family of circuits from one parameterised class
- Before you start
- Registers and clock edges. Scala is introduced where each chapter needs it. No other HDL is required.