Design concurrent hardware with rules

Run the smallest BSV program, a package with one module and one rule, and predict what it prints; then read a module with one register and one value method and the testbench that reads it, run it, and change one thing.

Tell a Bool from a Bit#(n), build and take apart bit vectors with concatenation, selection and reduction, and write a pure function that becomes combinational logic where it is called.

See why a sized value never changes width on its own, how an unsized literal takes the width of its target, and which function to call for zero extension, sign extension, truncation and reinterpretation.

Build combinational selection with the ?: operator, case and functions, give every path a value, and use the don't-care value ? only where no one can observe it.

Declare a register with mkReg, write it from one rule with <=, and see that a read inside the rule gives the start-of-cycle value while the written value appears in the next cycle.

Use a rule's explicit condition to hold a register, to stop a counter exactly at its limit, and to find the silent gap when the state one rule leaves never satisfies the condition of the next.

Put two rules in the same cycle: both fire when they touch different state, a second write to one register shadows the first with a warning, and a genuine conflict needs a read/write cycle; every firing is one atomic transition.

Tell the three method kinds apart by their result type, call them from rules, and see how a method's own readiness condition decides whether the calling rule fires at all.

Define a module with parameters, arguments and provisos, put a method's readiness condition in its header so that every calling rule stops when it is false, trace a stack through pushes and pops, and meet the conditions an interface needs at a synthesis boundary.

Define the types a design talks about with typedef: a synonym that only renames, an enum of named labels, a struct of named fields, and a tagged union that holds one alternative with its tag; compute their packed widths and read a union with pattern matching.

Name the states of a design with an enum, keep the current state in a register, write one rule per state whose guards never overlap, and predict a two-state machine cycle by cycle.

Turn a written requirement into an interface, one register and the action that updates it with the right priority, predict the behaviour with a model, then build and grade a clearable, enableable counter on your own.

How bsc splits source text into tokens, and the exact spelling rules for identifiers, keywords, comments, integer, Real and string literals, and compiler directives.

One file is one package; export decides which names leave it, import brings published names in, and a package boundary is a visibility boundary, not a hardware boundary.

A variable names a value rather than storing it, the declared type decides what an unsized literal means, and a loop with a constant bound unfolds into a fixed amount of hardware during elaboration.

Typeclasses name groups of overloaded operations, instances implement them per type, and provisos state the instances and width relations a polymorphic definition needs, all resolved at compile time with no selection circuit.

Take structured values apart with patterns: constants, variables, wildcards, struct and tagged-union patterns, pattern-matching case, pattern tests in conditions, and match declarations.

Build a rule as a Rules value, install it with addRules, and tell the one elaboration-time call apart from the many cycles the installed rule fires on.

The three phases that give a BSV design its meaning, elaboration, scheduling analysis and runtime, and the C, CF, SB and SBR relations primitive modules declare between their methods, which decide which calls may share a cycle.

Writing a multi-cycle process as a Stmt, running it with mkFSM, and reading its behaviour, one committed step per action in seq, loops with repeat, while and for, waiting with await, overlapping branches with par, and finishing only after a run that was started.

The library pieces most designs are built from, read as contracts, split and tuples whose boundary comes from the result type, FIFO methods whose implicit conditions make callers wait, FIFOF flags that report readiness as values, and system tasks that exist only in simulation.

Attributes as requests, proved claims and trusted claims, synthesize and noinline boundaries, port naming with always_ready and always_enabled, the scheduling attributes descending_urgency, execution_order, preempts and the rule assertions, and split, clock, reset and doc attributes.

The import "BVI" contract between typed BSV and external RTL, value and Action method mappings with enable and ready, default_clock and default_reset, schedule relations for every method pair, static parameters, and how to locate a failure in BSC compilation, Verilog elaboration or simulation.

Call a C function from BSV with import BDPI: the declaration, the carrier types each side sees, packed and wide values, polymorphic imports, return shapes, and how boundary failures look.