Learn RTL through signals and clocks

Read a half adder as a box with ports, learn the module and port declaration forms, predict what its testbench prints, run it, then change one wire and see the print change.

Bundle bits into a vector, pull ranges out of it, join pieces with braces, and learn what each operator family builds and how wide its result is, from bitwise, logical and reduction operators to arithmetic, shifts, comparisons and precedence, before rearranging a byte in Practice.

Write sized literals, know that an unsized one is at least 32 bits, read one bit pattern as signed or unsigned, and give an addition a target wide enough to keep its carry.

Tell nets from variables, write a multiplexer twice, as an assign with ?: and as an always @* with case, see why every path must assign the output, and use blocking = inside combinational blocks.

Describe a register with always @(posedge clock) and <=, learn the order of work inside one time step, read a counter trace to see the value before and after an edge, and watch a swap break when = replaces <=.

Give a register a synchronous reset and an enable, order the if/else chain so reset wins, and make a counter wrap where the requirement says rather than where the width runs out.

Chain registers into stages, learn what a testbench sees at the edge, after #1, with $strobe and in a waveform, start a VCD recording with $dumpfile and $dumpvars, give its times a unit with `timescale, and build a rising-edge detector whose pulse is exactly one cycle wide.

Place a module inside another as an instance, connect its ports by name, override a parameter per instance, run internal nets between instances, read a four-bit ripple-carry adder as a hierarchy, and recognize the elaboration errors and silent miswirings a connection list can hide.

Turn a state table into a state register, a next-state case and output logic, run a two-state rise detector and check its trace and waveform against the table, repair a broken transition, and design a three-state machine yourself.

Declare a memory as an array of registers, write it at the edge and read it asynchronously or through a register with one cycle of latency, then build a parameterized synchronous FIFO whose count, full and empty decide which pushes and pops take effect.

Write a testbench with reg inputs, wire outputs and a dut instance, make time pass with # delays, a clock and event controls, then package stimulus in a task, compare against a model with !==, and end a failing or hanging run with $fatal.

Choose which instances a VCD records with $dumpvars scopes and depths, read a waveform whose scopes skip a level, and recognize the mistakes that leave a recording empty, late, too shallow, off by a rounded delay, or missing an unnamed value.

Read a requirement into ports, widths, a select mapping, a priority order, a sampling time and boundary cases, predict the counter contract cycle by cycle, then write both checkpoint designs on your own.