15Verification

Read a register file in the same cycle

Problem

Intended behavior. RegFile holds eight 8-bit registers for a small processor. In the decode stage an instruction presents two source register numbers on raddrA and raddrB and needs both values in the same cycle, because the execute stage takes them at the next edge. A write on wen, waddr, wdata takes effect at the clock edge, so a read of the register being written in that cycle still returns the old value.

Current behavior. The starter compiles and stores every write. Its read ports, however, answer each instruction with the registers named by the previous instruction.

Your task. Find why the read ports lag and make both answer in the cycle of the request. Keep the ports and the write logic unchanged.

Read and predict

The testbench writes 10 * r + 1 into register r, so r3 holds 31 and r5 holds 51. It then presents one operand pair per cycle: (3, 5), (0, 7), (2, 2), (6, 1), and (6, 1) again.

Before running, write the rdataA and rdataB columns a correct register file produces. Then run the starter and line up its columns against yours. Notice which line is the only one where the starter agrees with you, and what is special about the address on that line.

Diagnose

Data that always belongs to the address presented one line earlier is the signature of a read port that registers its address. Decide which memory type in the starter has that read timing, and which memory type returns data in the same cycle with the same write behavior.

Run and explain

After changing the memory type, run again. Every line must show 10 * r + 1 for the register each port names, including the line where both ports name r2. Explain why the last line was the only one the starter got right, and why it no longer stands out.

Completion check

Both ports return the current contents of their registers in the cycle the register numbers are presented, for any pair of addresses, including the same register on both ports.
A write becomes visible from the cycle after its clock edge. In the write cycle, a read of that register returns the old value.
Writes and reads may happen in the same cycle without disturbing other registers.
Matching the public pairs is not enough: the operand pair changes every cycle in real use.

Hints

Hint 1

The last line repeats the previous pair. A lagging port only looks correct when its address does not change.

Hint 2

The memories chapter compares two read-write memories with identical write ports and different read latency. The register file needs the one with a combinational read.

Concept

A memory type is a timing contract, not only a storage choice. A synchronous-read memory can map to SRAM but delays data by one cycle, so logic that consumes the data in the same cycle needs a combinational-read memory. This register file stores 64 bits and needs read-selection logic; its physical implementation depends on the synthesis target.

Variation

Suppose decode were split across two cycles, with register numbers known one cycle earlier. Predict whether the starter's memory would then be correct, and which signal of the decoder would have to drive its read addresses.