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code0.HDL

11Implementation

Count rising edges, not high cycles

Problem

Intended behavior. EdgeCounter watches a one-bit input in. rise is true only in the first cycle of each high stretch, the cycle in which in is 1 after having been 0 in the previous cycle. count adds one at every such edge and wraps after 255. Reset defines the previous input as 0, so if in is already high when reset ends, that first cycle counts as one edge.

Current state. rise is just a renamed copy of in. The module has no memory of the previous cycle, so it cannot tell a new high stretch from one that is still going. The counter therefore counts high cycles, not edges.

Your task. Replace the TODO line with a definition of rise that compares the current input with the input from one cycle earlier. Keep the ports, the counter, and the testbench unchanged.

Read and predict

The public run pokes the pattern 1 1 0 1 1 1 0 0 1 0, prints rise and count for each cycle, then steps the clock. count on each line is the value before that cycle's edge.

Before running the starter, write down the rise column it will produce and the final count. Then write the columns a correct edge counter produces: rise should be 1 on exactly three lines, and the last line should show count=3. Cycle 0 is one of them, because the input before reset release is defined as 0.

Make the change

rise needs two values: what in is now, and what it was in the previous cycle. The previous value comes from a register that captures in at each rising edge. That register's reset value is part of the contract above.

Run again and compare with your prediction. A four-cycle high stretch must produce one pulse, and count must change one line after each pulse.

Completion check

  • rise is high for exactly one cycle per 0-to-1 transition, however long the input then stays high.
  • An input that is already high when reset ends counts as one edge.
  • count increments once per edge, wraps from 255 to 0, and clears on reset.
  • Matching the public pattern alone is not enough; any input sequence must produce the same relationship.

Hints

Hint 1

A combinational expression only sees the current cycle. Detecting a change over time needs state.

Hint 2

The sequential circuits chapter builds a one-cycle delay of an input with a single constructor that can also take a reset value. Compare in with that delayed copy.

Concept

An edge is a relation between two cycles, so its detector needs one register holding the older value. The register's reset value decides what the circuit assumes about the cycle before reset ended. Without one, the first comparison after reset depends on whatever the register happened to capture.

Variation

Predict the trace if rise detected falling edges instead. Which cycles of the public pattern would pulse, and what would the final count be?

Review this concept
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Main.scala