13Verification

Clear a sticky flag on reset

Problem

Intended behavior. ErrorMonitor watches an err input. seen turns on in the cycle after the first error and stays on, even when errors wraps back to 0, until the module is reset. errors counts error cycles modulo 16. Reset clears both outputs, and a module that has just come out of reset reports seen=0.

Current behavior. The starter compiles and counts correctly, but seen does not obey reset. After an error, a reset clears errors and leaves seen on. Even before the first error, the flag is not guaranteed to start off.

Your task. Find why the two registers react differently to the same reset, and make seen follow the contract. Keep the ports and the counter unchanged.

Read and predict

Read the two register declarations side by side. Both are updated under when(io.err), so their next-value logic is equally simple. The difference is in how each register was created.

The public run prints five phases: start, after two error cycles, right after one reset edge, one quiet cycle later, and after one new error. Predict both columns for a correct monitor before running. Then run the starter and find the line where seen and errors disagree about whether a reset happened.

Diagnose

The after-reset line is the key observation. A reset that clears one register and not the other is not a timing problem: reset applies only to registers that declare a reset value. Decide which declaration lacks one. The start line of the starter is not a reliable value either, because a register without a reset value has no defined starting state.

Fix, run, and explain

Change only the faulty declaration and run again. Both columns on the after-reset line must now read 0, and the new-error line must show the flag back on with a count of 1. Explain why the start line is now a guaranteed value rather than a lucky one.

Completion check

seen is 0 after reset, before any error.
seen turns on after the first error and stays on through quiet cycles and through the counter wrapping to 0.
A reset clears seen and errors together, including a reset asserted in a cycle where err is also high.
Deriving seen from errors is not a fix: sixteen errors bring the count back to 0 while the flag must stay on.

Hints

Hint 1

Compare the constructors used for seen and errors. Only one of them takes an initial value.

Hint 2

The reset table in the sequential circuits chapter shows a register created with Reg keeping its value through a reset edge. Create seen with the constructor that gives it a reset value of false.

Concept

Reset is not a global clear. It is part of each register's declaration. Control state such as valid bits, flags, and counters needs a reset value because correctness depends on where it starts. Pure data registers that are always written before use may skip reset.

Variation

Suppose errors were declared without a reset value as well. Predict the after-reset line, and explain why the public run could no longer show the defect by comparing the two columns.