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04Implementation

Keep the carry with +&

Problem

Intended behavior. CarryAdder adds two 4-bit unsigned inputs and drives a 5-bit sum. The fifth bit exists to hold the carry, so every pair from 0 + 0 to 15 + 15 must appear as its true value, up to 30.

Current behavior. Small sums are correct, but any sum of 16 or more comes out exactly 16 too small. The port is wide enough; the carry is lost before it reaches the port.

Task. Replace the expression on the TODO line so the carry survives. Keep all three port declarations as they are.

Read the starter

Read the port widths first, then the single connection. Answer two questions separately: what width does the expression on the right have, and what does a connection do when it drives a 5-bit sink from that width?

Predict before running

The public run pokes (3, 4), (9, 8), and (15, 15). For each row, write down what the starter prints and what a correct adder prints. Work 9 + 8 in binary: the true sum is 1_0001.

Run and explain

The starter prints 7, 1, and 14. Only the first row fits in four bits. For the other two, the addition produced a 4-bit result that had already discarded bit 4, and the connection then padded that result with a zero. Widening the sink cannot recover a bit that the expression never produced. A correct adder prints 7, 17, and 30.

Completion check

  • Every pair of 4-bit inputs produces its exact sum, not just the three printed rows.
  • sum carries the carry in bit 4 whenever the sum reaches 16.
  • The inputs stay 4 bits and sum stays 5 bits.

Progressive hints

Hint 1

The width of an addition is decided by the operator, before any connection sees the value. Look up the result width of + in the data types chapter.

Hint 2

Chisel has a second addition operator whose result is one bit wider than its widest operand. Only the operator changes; the operands stay the same.

Concept

+ keeps the operand width because a datapath adder usually wraps by design. +& keeps the carry because the answer needs it. A connection pads or truncates whatever width arrives, so the place to decide whether the carry exists is the operator, not the port.

Transfer experiment

Without editing the submission, imagine using subtraction with the same 4-bit inputs, a = 3 and b = 5. Predict what the ordinary and expanding subtraction operators would show on the 5-bit unsigned port, and explain why neither result is negative.

Review this concept
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Main.scala