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code0.HDL

05Implementation

Frame data with a parity bit

Problem

Intended behavior. ParityFrame turns seven data bits into an 8-bit frame for a link that checks even parity. Bits 6 to 0 of frame carry data unchanged. Bit 7 is the parity bit, chosen so that the frame as a whole contains an even number of ones. data = 0x01 therefore becomes 0x81, while data = 0x03 already has two ones and stays 0x03.

Current behavior. The starter connects data straight to frame. The connection pads the 7-bit value with a zero, so bit 7 is always 0 and every frame whose data holds an odd number of ones breaks the parity rule.

Task. Replace the connection on the TODO line. Keep both port widths.

Read the starter

Two separate questions decide the frame. Which operator collapses all bits of a value into one bit that is 1 when the count of ones is odd? Which operator joins two values, and which of its arguments ends up in the high bits?

Predict before running

The public run prints frames for 00, 01, 03, 55, and 7f. Count the ones in each data value, decide bit 7, and write each correct frame in hex before you run. The starter prints every frame equal to its data.

Run and explain

After the change, the rows read 00, 81, 03, 55, and ff. 0x55 is 101_0101, four ones, so its parity bit is 0. 0x7f has seven ones and needs a parity bit of 1, which makes the frame ff. If 81 appears as 03 instead, the parity bit landed at the bottom and the data moved up one position.

Completion check

  • All 128 data values produce a frame with an even number of ones.
  • data appears unchanged in bits 6 to 0, and the parity bit occupies bit 7.
  • frame stays exactly 8 bits wide, with nothing truncated.

Progressive hints

Hint 1

Even parity is the same as asking whether the data already holds an odd number of ones. The operators chapter lists three reductions; one of them answers that question.

Hint 2

Cat places its first argument in the most significant bits. A 1-bit value joined above a 7-bit value is exactly 8 bits wide.

Concept

xorR reduces the data bits to one Bool using XOR logic, and Cat lays values side by side using wiring in argument order. The result width of Cat is the sum of its argument widths, so the frame fits the port exactly.

Transfer experiment

Suppose the link checked odd parity instead. Predict the frame for data = 0x00 and data = 0x7f, and name the single extra operator the parity bit would need.

Review this concept
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Main.scala