07Waveforms and time

1. A waveform draws each signal on one row along a time axis

A waveform records what value each signal had at each moment. Time runs along the horizontal axis from left to right, and every signal gets one row. The rising edge of the clock clk is the reference against which every other row is read.

The waveform below shows the register d → q from the previous unit over six cycles. One cycle is eight characters wide, and the gap between two cycles is a rising edge. The edge numbers are written under the edge row.

cycle       0        1        2        3        4        5
clk      ‾‾‾‾____ ‾‾‾‾____ ‾‾‾‾____ ‾‾‾‾____ ‾‾‾‾____ ‾‾‾‾____
edge             ^        ^        ^        ^        ^        ^
                 0        1        2        3        4        5
d        00000000 11111111 11111111 00000000 11111111 00000000
q        00000000 00000000 11111111 11111111 00000000 11111111

Cycles and edges are numbered by one rule.

Read the q row with that rule. During cycle 1, d is 1; edge 1, which ends cycle 1, stores that 1; so q is 1 from cycle 2 on. The q row is the d row shifted one cycle to the right, and that shift is the register's one-cycle delay.

The lab tables and the waveform line up like this: the "before the edge" column is the value visible during that cycle, and the "after the edge" column is the value visible during the next cycle. In cycle 1 the table says "q after the edge: 1"; in the waveform, q is 1 during cycle 2. They are the same fact.

2. Inputs are driven in the cycle, sampled at the edge, observed after it

A cycle contains three distinct moments.

After the simulator has processed the register updates scheduled for an edge, Q shows the new value. Before the edge it still shows the old value. A testbench that reads in the same simulation instant must respect that event ordering; merely detecting the edge does not guarantee the update is done. Combinational connections do not wait for a clock edge.

Caution. In a zero-delay RTL simulation, a register output can change at the same timestamp as the edge, with no visible gap. Real hardware has a clock-to-Q delay: a short time after the edge before Q settles. The order in which a simulator processes events within one instant is not a model of that physical delay, so do not read a zero-width change in a waveform as "hardware that switches instantly".

3. One register stage delays by one cycle, two stages by two

In delay2, two registers in a row, the next value of s1 is in and the next value of s2 is the current value of s1. In the waveform the s1 row is the in row shifted right by one cycle, and the s2 row by two.

cycle       0        1        2        3        4        5
clk      ‾‾‾‾____ ‾‾‾‾____ ‾‾‾‾____ ‾‾‾‾____ ‾‾‾‾____ ‾‾‾‾____
edge             ^        ^        ^        ^        ^        ^
                 0        1        2        3        4        5
in       11111111 00000000 11111111 11111111 00000000 00000000
s1       00000000 11111111 00000000 11111111 11111111 00000000
s2       00000000 00000000 11111111 00000000 11111111 11111111

Two numbers describe such a chain, and they must be kept apart.

Adding stages lengthens the wait but does not slow the flow: a new value enters every cycle and one value leaves every cycle. In the experiment, change in every cycle while pressing edges and watch the same value appear one cycle later on s1 and another cycle later on s2.

Now fill in the missing waveform. From the in column, write s1 and s2 after each edge. Both registers start at 0 in cycle 0.

4. Find the first cycle where two waveforms differ

To compare waveforms, find the first cycle that differs and then look at how the rest differs. The two tables below show s2 of delay2 for the same in. The first is the expectation computed from the requirement; the second was observed by simulating some design. Both list values after the edge.

5. Variation: a rising-edge detector

In the cycle-by-cycle model, inputs are held constant throughout each cycle. Under that assumption, rise-detect turns a 0-to-1 change of the input into a pulse one cycle long. The register prev remembers last cycle's in, and the output rise is 1 when in is 1 and prev is 0.

Because rise is not a register, it does not wait for an edge. It becomes 1 in the very cycle in goes to 1, and when the next edge updates prev to 1 it falls back to 0 for the same in. In the lab table the rise column is the value during the cycle, not a value after the edge. Raise in to 1 and press several edges: rise is 1 in the first of those cycles only. If a physical input changes partway through a cycle, this combinational pulse need not last a full period.

6. Summary

• A waveform has time along the horizontal axis and one row per signal; the rising edge of clk is the reference for reading it.
• Edge n ends cycle n, and cycle 0 starts from the initial value. In the lab tables, "before the edge" is the value visible during that cycle and "after the edge" the value visible during the next.
• Inputs are driven during the cycle, sampled at the edge, and observed after the edge.
• In a simulator's waveform a register output changes at the edge itself; real hardware has a clock-to-Q delay.
• n register stages raise the latency to n cycles and leave the throughput unchanged.
• Compare two waveforms from the first cycle that differs.

The next chapter takes a requirement apart into test cases, separates the roles of the design and its testbench, and reasons from a first mismatch to a likely cause.