1. A gate is a rule from input bits to an output bit
A logic gate is a basic combinational element that computes an output bit from its inputs. The gates introduced here have one or two inputs and no stored state. In the ideal model, the output follows the current inputs; physical gates take a propagation delay to respond.
We start with four gate functions.
| Gate | Output is 1 when | Read it as |
|---|---|---|
| NOT | the input is 0 | the opposite |
| AND | both inputs are 1 | both |
| OR | at least one input is 1 | either |
| XOR | the inputs differ | different |
In the experiment below, press a and b to flip them between 0 and 1 and find the combination that
makes y 1. The row of the table that matches the current inputs is marked as you go.
Concept experiment · and
A browser model of the circuit, not a compiled design. The real toolchain runs in the examples.
Inputs
Outputs
- y
- 0
| a | b | y | current inputs |
|---|---|---|---|
| 0 | 0 | 0 | ◂ current inputs |
| 0 | 1 | 0 | |
| 1 | 0 | 0 | |
| 1 | 1 | 1 |
2. A truth table states the whole rule
A truth table lists every possible combination of the inputs, one per row, and the output for each. With n inputs there are 2^n rows: four for two inputs, eight for three.
A truth table describes the stable binary input-output function of a combinational circuit. Two circuits with the same table give the same settled output for each input, though their delay, area and power use can differ.
Build the XOR table yourself: press through all four combinations, read y, and confirm in the table
that exactly two rows give 1.
Concept experiment · xor
A browser model of the circuit, not a compiled design. The real toolchain runs in the examples.
Inputs
Outputs
- y
- 0
| a | b | y | current inputs |
|---|---|---|---|
| 0 | 0 | 0 | ◂ current inputs |
| 0 | 1 | 1 | |
| 1 | 0 | 1 | |
| 1 | 1 | 0 |
Check
With a = 1 and b = 0, what is a XOR b?
Check
How many rows does the truth table of a three-input circuit have?
3. From a condition in words to a logic expression
Requirements arrive in words. The word that joins the conditions tells you the gate.
| The requirement says | Gate |
|---|---|
| … and … | AND |
| … or … | OR |
| not … | NOT |
| the two differ | XOR |
| the two are equal | XNOR (XOR inverted) |
| both are 0 | NOR (OR inverted) |
If an alarm must sound "when the door is open (door = 1) and the system is armed (armed = 1)",
the expression is alarm = door AND armed: both conditions have to hold, so the gate is AND. "When
the door or the window is open" is OR.
Caution. After writing the expression, check all four rows of its truth table. The requirement may be silent about a combination, such as "door closed, system armed", and the expression still has to give the value you intend there.
Check
The output must be 1 only when the two inputs are equal. Which operation do you choose?
Check
NAND is AND with its output inverted. With a = 1 and b = 1, what is a NAND b?
4. Variation: a three-input majority
A three-input circuit reads the same way. Below is a full adder; its cout is a majority output,
1 when two or more of a, b and cin are 1. Press through all eight rows and count the ones where
cout is 1. sum is the subject of the next unit.
Concept experiment · full-adder
A browser model of the circuit, not a compiled design. The real toolchain runs in the examples.
Inputs
Outputs
- sum
- 0
- cout
- 0
| a | b | cin | sum | cout | current inputs |
|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 | ◂ current inputs |
| 0 | 0 | 1 | 1 | 0 | |
| 0 | 1 | 0 | 1 | 0 | |
| 0 | 1 | 1 | 0 | 1 | |
| 1 | 0 | 0 | 1 | 0 | |
| 1 | 0 | 1 | 0 | 1 | |
| 1 | 1 | 0 | 0 | 1 | |
| 1 | 1 | 1 | 1 | 1 |
Check
How many of the eight input combinations have two or more inputs equal to 1?
5. The same gates in each language
The three languages spell the same gates differently. Nothing here needs memorising; each language's chapters introduce the operators when they are used.
| Gate | Verilog | BSV | Chisel |
|---|---|---|---|
| NOT | ~a (bits), !a (logical) | ~a (Bit), !a (Bool) | ~a (UInt), !a (Bool) |
| AND | a & b, a && b | a & b, a && b | a & b, a && b |
| OR | a | b, a || b | a | b, a || b | a | b, a || b |
| XOR | a ^ b | a ^ b | a ^ b |
Note. Later chapters distinguish bitwise and logical operators. For known one-bit values, the corresponding operations give the same 0 or 1, but each language has its own operand and result types.
6. Summary
- A gate does not remember. Its output is a function of the present inputs.
- A truth table has one row per binary input combination and describes the circuit's settled logic function, not its physical timing.
- "and" becomes AND, "or" becomes OR, "not" becomes NOT, "differ" becomes XOR.
- After writing an expression, check every row of its table.
The next chapter joins gates into circuits that select and add bits.