06Clock, reset and enable

1. The clock repeats, and a register moves only at the rising edge

A clock is a signal that alternates between 0 and 1 at a fixed rate. The moment it goes from 0 to 1 is a rising edge, and the time from one rising edge to the next is the period. One period is a clock cycle. The registers in this chapter update at rising edges, so we track their state one edge at a time; combinational signals can still change between edges.

With a 10 ns period, three cycles take 30 ns. In the ideal model, an initial state and the inputs at each edge determine the register's state. Physical inputs must also satisfy setup and hold timing around the edge. The experiments assume that timing is met and predict state by counting edges.

The experiments in this unit number cycles from 0. Cycle 0 begins with the register holding its initial value and ends with edge 0. Each row of a table is one cycle: the column "inputs sampled at the edge" holds what the inputs were just before that edge, and "after the edge" holds what that edge stored.

Note. The register model of this primer is fixed: one clock, rising edge, synchronous clear. Falling-edge registers and designs with several clocks appear in the language lessons where they are needed.

2. Enable chooses between updating and holding

An enable tells a register whether this edge should store anything. With en = 1 the edge stores d; with en = 0 the edge comes and goes and the register keeps its current value.

The enable does not add a second moment of storing: the edge is still the only one. In the experiment, leave en at 1, change d several times (0, 1, 0, 1), and press the edge once. Only the d present at the edge reaches q. Then lower en to 0, change d and press more edges. q stays where it is.

Caution. With en = 0, changing d does not affect the stored value. In a feedback-MUX implementation, the register's next value is its current q, rather than the external d.

3. A reset returns a register to a chosen value

A reset makes a register take a value chosen by the designer when the reset condition applies. A register without reset or explicit initialization typically starts as x in a four-state RTL simulation. A reset input alone does not initialize it until that reset is applied. When reading a reset circuit, check its timing, polarity and priority relative to other updates.

In this unit's counter, counter4, the clear input is a synchronous, active-high functional clear. When clear is 1 at an edge, q becomes 0 whatever enable says; only when clear is 0 does enable choose between counting and holding. The count runs from 0 to 15 and wraps to 0 after 15.

Take q = 2 and an edge with clear = 1 and enable = 1: the next value is 0, not 3. If the next cycle has clear = 0 and enable = 1, the count goes from 0 to 1. The table below writes this out cycle by cycle.

Reproduce it in the experiment: set enable to 1 and press two edges, raise clear as well and press one edge, lower clear and press one edge, lower enable and press one more. The "after the edge" column of the lab table should match the table above.

Note. The default reset differs by language. The Verilog that the BSV compiler generates has a synchronous, active-low reset (RST_N) by default. Chisel's default reset is synchronous and active-high. In Verilog the reset is whatever the code says: checking the reset only at the clock edge makes it synchronous, and reacting to the reset signal's own change as well makes it asynchronous. Each language path shows how that is written.

4. Fill in the state table

The clear and enable columns are the values sampled at each cycle's edge. Write q after the edge. Cycle 0 starts with q = 0, and the compare button names the first cycle that differs.

5. Variation: a register that captures and keeps a value

Enables are not only for counters. To take a sensor reading at one chosen moment and keep it unchanged until the next, one register whose en is raised only at that moment is enough. While en is 0, d may change as it likes; q keeps the last value that was captured.

In the table, d is the sensor and en marks the capture moments. Write q after each edge.

6. Summary

• The clock repeats and a register stores only at the rising edge. One cycle runs from one rising edge to the next, and the experiments number cycles from 0.
• However an input moves between edges, only its value at the edge is stored.
• Enable picks the next value: d (update) or the current q (hold).
• Resets are described by kind (synchronous or asynchronous), polarity (active-high or active-low) and priority (before enable). The clear of counter4 is synchronous, active-high and wins over enable.
• Default resets differ by language; follow each language path's description.

The next chapter draws these tables along a time axis as waveforms and separates the moment inputs are driven from the moment outputs are observed.