1. A combinational circuit cannot remember
Every circuit so far has been combinational: its output is a function of the inputs it has right now, and when an input changes the output changes with it. A counter, which "adds one to the previous value", cannot be built that way. The previous value has to live somewhere, and a combinational circuit has nowhere to keep it.
In the synchronous circuits here, a register holds a value between clock edges. The values held in a circuit's registers are its state, and a circuit with state is a sequential circuit.
| Kind | Output depends on | Storage | Examples |
|---|---|---|---|
| Combinational | the present inputs | none | AND, multiplexer, adder |
| Sequential | the present inputs and the stored values | registers | counter, state machine |
2. A register copies D to Q at the edge
A register has an input D and an output Q. The moment the clock signal goes from 0 to 1 is a rising edge. The registers in this unit store the value of D only at a rising edge and hold it on Q until the next edge. Between edges D may change as often as it likes; Q does not follow.
In the experiment, change d, then press Clock edge. q does not move when d changes; it moves
only after the edge, and then it shows what d was.
Concept experiment · dff
A browser model of the circuit, not a compiled design. The real toolchain runs in the examples.
Inputs
Outputs
- q
- 0
No edge has happened yet. Set the inputs, then apply a clock edge.
Each row of the table is one edge. The "before the edge" column is q before that edge happened; the
"after the edge" column is q once the edge has copied D. Comparing the columns shows the state
update caused by that edge.
Note. This unit covers one register on one clock, updated on the rising edge. Registers that act on the falling edge, and asynchronous resets that change a value with no edge at all, are introduced where the next unit and the language lessons need them.
Check
d has just gone from 0 to 1. When does q become 1?
Check
With no edge at all, d goes 0, 1, 0. What does q do?
3. The current value and the next value are two values
Designing a sequential circuit means distinguishing two roles. The current and next values can be equal, as they are when a register holds its value.
| Name | Meaning | Where it is |
|---|---|---|
| Current value | What the register holds now; read it at Q | inside the register |
| Next value | What the next edge will store; computed from the current value and the inputs | the combinational logic feeding D |
The part that computes the next value is combinational. When the edge comes, the register stores it,
and from that moment on it is the new current value. The smallest example is a toggle: when t is 1
the next value is the inverse of the current one; when t is 0 the next value equals the current one.
Concept experiment · toggle
A browser model of the circuit, not a compiled design. The real toolchain runs in the examples.
Inputs
Outputs
- q
- 0
No edge has happened yet. Set the inputs, then apply a clock edge.
Caution. Placing the next value on D does not change Q. Q changes only at the edge, so reading Q within the same cycle still gives the current value. That one-edge gap is not a bug; it is what a register is.
Check
The toggle's current q is 1 and t is 1. After one edge, what is q?
4. Fill in the state table
Now fill in a table yourself. The d column is the value on the register's input during each cycle.
Write what q will be after the edge that ends that cycle. The compare button names the first cycle
that differs from the model.
Predict, then compare · dff
Fill in each cell before comparing. Empty cells count as a mismatch.
| Cycle | dinputs sampled at the edge | qafter the edge |
|---|---|---|
| 0 | 1 | |
| 1 | 1 | |
| 2 | 0 | |
| 3 | 1 | |
| 4 | 0 | |
| 5 | 0 |
5. Variation: two registers in a row
One register delays a value by one edge. Two registers in a row delay it by two. Read the in column
and write the value each register, s1 then s2, holds after the edge. The next value of s2 is
the current value of s1, not in.
Predict, then compare · delay2
Fill in each cell before comparing. Empty cells count as a mismatch.
| Cycle | ininputs sampled at the edge | s1after the edge | s2after the edge |
|---|---|---|---|
| 0 | 1 | ||
| 1 | 0 | ||
| 2 | 0 | ||
| 3 | 1 | ||
| 4 | 1 | ||
| 5 | 0 |
6. Summary
- A combinational circuit does not remember. Needing the previous value means needing a register.
- A register stores D at the rising edge and holds it on Q until the next edge.
- The current value is read at Q; the next value is computed by combinational logic and placed on D. The two are one edge apart.
- Registers in a row delay a value by one edge each.
The next chapter covers the clock's period and cycles, the reset that returns a register to a known value, and the enable that lets it hold.