08Verification

Let reset win over enable

Problem

Intended behavior. event_counter is a 4-bit counter with an enable input and a synchronous, active-high reset. At each rising edge, reset high clears count to 0 whether or not enable is high. Otherwise count advances by one when enable is high and holds its value when enable is low.

Current behavior. The starter compiles and counts correctly while enable is high. The public testbench raises reset at cycle 8 while enable is low, yet count stays at 4 and later resumes from 4 instead of from 0.

Your task. Find the defect in the always block and correct it. Keep the ports, the synchronous reset, and the public testbench unchanged.

Read the trace

The testbench changes its stimulus on falling clock edges and prints on rising edges. Each line shows the inputs the design sampled at that edge and the count it held just before the edge. A reset sampled at cycle 8 should therefore show count=0 on the cycle 9 line.

Before editing, write the expected count column for cycles 8 to 13 for a correct design. Then trace the starter's nested if statements with reset=1 enable=0 and identify which branch runs. The accumulator in the Testbench chapter's self-check example settles the same kind of priority with its clear input.

Restructure the block, run, and check cycles 8 to 13 against your column. Then explain why cycles 0 to 7 print the same values before and after the fix: in those cycles reset is only ever high while enable is high too.

Completion check

reset clears the counter on a rising edge for both values of enable, including immediately after power-up when the register holds no value yet.
Reset takes effect at the rising edge, not at the moment the input rises.
With reset low, enable alone decides between incrementing and holding, and the 4-bit count wraps from 15 to 0.

Progressive hints

Hint 1

The two conditions are not equals. One of them must be checked before the other regardless of the second one's value.

Hint 2

In the starter, reset is only examined inside the branch where enable is already high. Ask what happens to a reset that arrives in the other case.

Hint 3

Restructure the block as one if/else if chain whose first test is reset. Adding reset to the sensitivity list would make it asynchronous, which this counter must not be.

Transfer experiment

Suppose the testbench held enable low from time 0. Predict what the starter would print for every line and why x appears. Then explain why a reset that depends on another input cannot be trusted to initialize a register.